Life of a Launch II, now part of chapter 2, tells the same story as one continuous shot, narrated by the thread itself, with a real-time clock and optional sound.
The film follows one kernel launch on your RTX 5070, vecadd<<<1024, 256>>>, and one thread inside it: element 2,690, which is thread 130 of block 10, lane 2 of warp 4. It zooms from the CPU down to that lane and back out. The captions carry the explanation; the plates show it happening. Space plays and pauses, ← → jump between scenes, j / l move five seconds.
Pause whenever a caption makes a claim, and check it against the picture. Every scene is one tab of chapter 2’s pseudocode:
| Scene | What happens | Where it’s explained |
|---|---|---|
| 1 · Launch | host code, asynchronous launch, data stays in VRAM | ch. 2 §1 |
| 2 · Grid | blocks, threadIdx, cutting a block into warps, lane and warp IDs | ch. 2 §3–4 |
| 3 · Place | blocks onto SMs, the four budgets, waves and the tail, scalability | ch. 2 §3, §9 |
| 4 · SM | quadrants, warps dealt to schedulers, occupancy | ch. 2 §6, §9 |
| 5 · Schedule | one issue per cycle, latency hiding, stalls at low occupancy | ch. 2 §8, ch. 1 §3 |
| 6 · Issue | SIMT, uniform and divergent branches | ch. 2 §7 |
| 7 · Fetch | 32-byte sectors, coalesced vs strided, shared-memory banks | ch. 3 |
| 8 · Done | completion, and the five moves |
Memory latency is shortened to 18 cycles in scene 5 so it fits on screen (on your card it is several hundred). Block completion times are jittered by hand, not measured. The scheduler picks the least recently issued ready warp, a reasonable stand-in for NVIDIA’s unpublished policy. Everything else (48 SMs, 6 blocks per SM for this kernel, 12 warps per scheduler, 32-byte sectors, 32 banks) is your card’s real configuration.